Mcuzone 野芯科技

标题: 树莓派Raspberry Pi 5发布，16nm BCM2712处理器，2.4GHz四核A76 [打印本页]
作者: Mcuzone_Robin    时间: 2023-10-4 11:42
标题: 树莓派Raspberry Pi 5发布，16nm BCM2712处理器，2.4GHz四核A76
关键词： 树莓派 Raspberry Pi 5  博通  BCM2712  16nm制程 四核2.4GHz Cortex-A76概述：树莓派基金会在9月28号发布Raspberry Pi 5，其基于博通16nm工艺四核2.4GHz Cortex-A76内核BCM2712处理器。具体规格和图片我们来看一下官方信息：

Key features include:

作者: Mcuzone_Robin    时间: 2023-10-4 11:42

作者: Mcuzone_Robin    时间: 2023-10-4 11:45
来看一下关于BCM2712的官方描述：
BCM2712 is a new 16-nanometer application processor (AP) from Broadcom, derived from the 28-nanometer BCM2711 AP which powers Raspberry Pi 4, with numerous architectural enhancements. At its heart is a quad-core 64-bit Arm Cortex-A76 processor, clocked at 2.4GHz, with 512KB per-core L2 caches, and a 2MB shared L3 cache. Cortex-A76 is three microarchitectural generations beyond Cortex-A72, and offers both more instructions per clock (IPC) and lower energy per instruction. The combination of a newer core, a higher clock speed, and a smaller process geometry yields a much faster Raspberry Pi, and one that consumes much less power for a given workload.
Our newer, faster CPU is complemented by a newer, faster GPU: Broadcom’s VideoCore VII, developed here in Cambridge, with fully open source Mesa drivers from our friends at Igalia. An updated VideoCore hardware video scaler (HVS) is capable of driving two simultaneous 4Kp60 HDMI displays, up from single 4Kp60 or dual 4Kp30 on Raspberry Pi 4. A 4Kp60 HEVC decoder and a new Image Sensor Pipeline (ISP), both developed at Raspberry Pi, round out the multimedia subsystem. To keep the system supplied with memory bandwidth, we have a 32-bit LPDDR4X SDRAM subsystem, running at 4267MT/s, up from an effective 2000MT/s on Raspberry Pi 4.


作者: Mcuzone_Robin    时间: 2023-10-4 11:48
不同于4B上的BCM2711，外设扩展用的是第三方的芯片VL805，在BCM2712上树莓派采用了一款自主设计的RP1接口芯片，下面我们来看一下关于RP1的描述：
RP1
Previous Raspberry Pi generations were built on a monolithic AP architecture: while some peripheral functions were provided by an external device (the Via Labs VL805 USB controller and hub on Raspberry Pi 4, and the Microchip LAN951x and LAN7515 USB hub and Ethernet controller chips on earlier products), substantially all of the I/O functions were integrated into the AP itself. Fairly early in the history of Raspberry Pi, we realised that as we migrated the AP to progressively newer process nodes, this approach would eventually become both technically and economically unsustainable.


Raspberry Pi 5, in contrast, is built on a disaggregated chiplet architecture. Here, only the major fast digital functions, the SD card interface (for board layout reasons), and the very fastest interfaces (SDRAM, HDMI, and PCI Express) are provided by the AP. All other I/O functions are offloaded to a separate I/O controller, implemented on an older, cheaper process node, and connected to the AP via PCI Express.
RP1 is our I/O controller for Raspberry Pi 5, designed by the same team at Raspberry Pi that delivered the RP2040 microcontroller, and implemented, like RP2040, on TSMC’s mature 40LP process. It provides two USB 3.0 and two USB 2.0 interfaces; a Gigabit Ethernet controller; two four-lane MIPI transceivers for camera and display; analogue video output; 3.3V general-purpose I/O (GPIO); and the usual collection of GPIO-multiplexed low-speed interfaces (UART, SPI, I2C, I2S, and PWM). A four-lane PCI Express 2.0 interface provides a 16Gb/s link back to BCM2712.
Under development since 2016, RP1 is by a good margin the longest-running, most complex, and (at $15 million) most expensive program we’ve ever undertaken here at Raspberry Pi. It has undergone substantial evolution over the years, as our projected requirements have changed: the C0 step used on Raspberry Pi 5 is the third major revision of the silicon. And while its interfaces differ in fine detail from those of BCM2711, they have been designed to be very similar from a functional perspective, ensuring a high degree of compatibility with earlier Raspberry Pi devices.





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